8051SBC V1.0

I decided to rename C52EVB to be 8051SBC. Since the cpu can be any 8051 compatible chips with 40-pin DIP package. The old day chips, say 8031, 8751, 8032 or the new chips, 89C51, 89C52, 89C51RD2 can be used without any problem. Some may think that your old chips were useless, now you can use it for many projects. The monitor program of new 8051SBC was placed at external 32kB EPROM. With this space, you can customize your own monitor code or even add the application program and have the DIP switch to boot it when power up. The 32kB SRAM still be mapped as external code and data memory. We can test the program in RAM, when it firms then put it in the space in EPROM. The memory and i/o decoder is now using GAL (Generic Array Logic).

The hardware schematic was provided to be an exemplary design for student to learn basic design of 8-bit microprocessor board. The board is a generic tool for every microprocessor lab. I provided all materials in public domain, so you may build it for your lab. Student can learn assembly programming, HLL programming and hardware interfacing.


The new 8051SBC features;

CPU: Any 8051 compatible with 40-pin DIP package @11.0592MHz

MEMORY: 27C256, 32kB EPROM for monitor program

62256, 32KB SRAM for both code and data space

I/O: direct cpu bus interface 2x16 line LCD

8-bit input port, 74LS244

8-bit output port, 74HC573

MEMORY and I/O Decoder: GAL16V8D

EEPROM: 24LC256, 32KB serial eeprom

RTC: Real-time clock, DS1307 with +3V Lithium backup

ADC: LTC1298, SPI interface 2-channel 12-bit Analog-to-Digital Converter

I/O pins: P1,P3 of 8051 cpu, 16-bit I/O port

Debug LED: single dot LED connected to P1.7

Keypad and DIPSW: 4-bit keypad and 4-bit DIP switch

RS232 Level Converter: MAX232

RS485: 75176 differential transceiver

Serial Interface: 9600 8n1

Monitor Program: Modified PAULMON2 including new commands

Hardware Schematic

Complete schematic for cpu and memory is shown in Figure 2. U7 is 40-pin 8051 compatible chip. The xtal is 11.0592MHz. JP1 selects internal or external code memory. With the external monitor mode, we make EA# to GND. The data bus D0-D7 are tied to memory chip, U1, U2 and to the GPIO, U3, U4 directly. Both memory chips are 32kB, so each chip needs A0-A14. A15 is used for memory decoder that decodes between first 32kB and second 32kB of external code memory. When A15 = 0, U1 the monitor rom was selected. The OE# of U1 is tied to PSEN#, so the code memory will enable only when address range 0x0000-0x7FFF of code memory are accessed. The upper memory space from address 0x8000-0xFFFF makes A15 = 1. When A15 = 1, U2 or SRAM will be selected. This memory space was decoded to be overlapped between external data and code memory. So while running under monitor mode, we can then load the hex code into the SRAM(data memory) and when JUMP from monitor program to address says 0x8000, the PSEN# that AND with RD# and ties to OE# of SRAM will enable the RAM to be code memory.